Simulation Based Execution Time Analysis of SDF Applications on Heterogeneous MPSoCs Using Measured Delay Distributions


Embedded computers become more and more part of the everyday life. With the boom of the Internet-of-Things the amount of those small computer systems increased tremendously. Also the complexity of tasks they have to do changed from simple control algorithms to image-processing, video-processing or even Artificial Intelligence. Therefore heterogeneous multi-processor systems on a chip (HMPSoCs) are commonly used. To increase power and cost efficiency, a trade-off between the resources of the hardware and the needs of the software must be found. While optimizing the mapping of the software on the hardware components the performance impact must be evaluated to guarantee a certain quality of service. Classical formal analysis methods are too compute intensive, even for dual core systems. Simulation based approaches can improve the scalability.
In my work, I use a simulation based approach to analyze timing behavior of software executed on HMPSoCs. Therefore I use the distribution of execution times for the performance model. This method provides a more realistic estimation of the execution times of an application. Goal of this work is, to provide a suitable method for design space exploration of HMPSoCs. For my approach strict models are used for designing the hardware and software. This reduces the complexity of the performance analysis. The hardware is a set of composable tiles with private memory for instructions and local data. The software model differentiates between computation and communication phases. This allows to determine when and where interference can happen. To characterize the system, the execution time of computation phases of the software components get measured. By keeping the distribution of execution times instead of just abstracting the data to best-case and worst-case delay, the analysis results are more representative to the actual behavior of the real system. The shared resources like communication interface and shared memory get modeled in detail.
For evaluation, a heterogeneous MPSoC with up to 7 processing elements is used. This MPSoC is used to run different applications like a Sobel-Filter (simple example) and a JPEG-Decoder (computation intensive). For the evaluation the analyzed performance gets compared to measured execution times of the same mapping. Therefore the execution time from the beginning to the end of an iteration of sample applications gets analyzed and measured. This is done for various applications with different mappings for several hardware configurations.
The proposed analysis method allows an insight into the distribution of possible mappings for an application on an HMPSoC. This method can be used for design space exploration (DSE) of soft real-time application.
Betreuer: Prof. Dr. Wolfgang Nebel


09. Dezember 2019, 16:00


Ralf Stemmer, Universität Oldenburg


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