[Seminar 27.03.2019] Adolf
Prof. Dr. Ernst-Rüdiger Olderog,
Department of Computing Science, FK II, University of Oldenburg,
D-26111 Oldenburg, Germany
Microelectronic components for ICT-Systems experience increasing aging stress due to Negative Bias Temperature Instability (NBTI). NBTI leads to a threshold voltage degradation which results in larger signal delays after some years of usage. Thus timing constraints, defined by the system specification, may be violated in field, leading to malfunction of ICT-components. NBTI is caused by imperfections in the gate oxide of PMOS-transistors. The state-of-the-art explanation of NBTI is given by the four-state-trap model, which describes aging as charge trapping under negative bias stress. With NBTI being recoverable and heavily depending on the stress history, it is very difficult to take aging into account during design time.
The aim of this work is to provide an abstract description of the occupation state of trap-ensembles of a single PMOS-transistor in the first step. The idea is to obtain the collective trap-states of a single transistor under varying stress conditions without the need to simulate all traps over time. The abstraction relies on the ideas CET-Maps and the Phase Space Model. At the end of the simulation the occupation state for all traps shall be estimated. Thus the threshold voltage degradation can be obtained.